1. Field of the Invention
The present invention generally relates to processors such as microprocessors, and more particularly to a microprocessor having a test circuit for performing a burn-in test in order to identify a device having an initial fault and eliminate such a device.
Recently, it has been required that less-expensive microprocessors be developed in a short time. The short-term development of microprocessors has been attempted by automatically performing the design tasks of the device specification, description of device functions, logic synthesis and layout. The reduction in the production cost has been attempted by optimizing the chip floor plan taking into account reduction in the chip area and the test circuit.
Before microprocessors are delivered by manufacturers, a function test and a burn-in test are performed by utilizing test circuits in order to ensure reliability of the delivered microprocessors. In order to efficiently perform these tests, it is preferable to equip microprocessors with built-in test circuits. However, the built-in test circuits will lead to an increase in the chip area.
2. Description of the Prior Art
A conventional microprocessor has an external terminal used to select a burn-in test mode, and a circuit configuration capable of testing almost all transistors formed in the microprocessor by means of a clock input signal. Also, the burn-in test for a microprocessor having a built-in micro-ROM is performed by allowing the micro-ROM to freely run, whereby almost all transistors of the microprocessor can be tested. A microprocessor which does not have a micro-ROM is equipped with a latch circuit with a scan-in terminal supplied with a scan-in signal in order to perform the internal logic operations. A microprocessor which does not have a micro-ROM is also tested by another testing method in which instructions are issued at random by a built-in controller in order to perform the internal logic operations.
FIG. 1 shows a conventional master/slave latch circuit with a scan-in terminal, and FIG. 2 shows a conventional master/slave latch circuit. In FIGS. 1 and 2, IN denotes an input signal in a normal operation, SIN denotes a scan input signal, and OUT denotes an output signal. Each of the master/slave latch circuits shown in FIGS. 1 and 2 includes clocked CMOS inverters 1 and 2, each of which receives complementary control signals C and CX which enable and disable each of the CMOS inverters 1 and 2. Further, each of the latch circuits shown in FIGS. 1 and 2 includes CMOS inverters 3, 4, 5 and 6. The latch circuit shown in FIG. 1 includes transfer gates 7 and 8. The transfer gate 7 is made up of a P-channel MOS transistor 9 and an N-channel MOS transistor 11, and the transfer gate 8 is made up of a P-channel MOS transistor 10 and an N-channel MOS transistor 12. The transfer gate 7 is turned ON and OFF by complementary control signals CA and CAX, and the transfer gate 8 is turned ON and OFF by complementary control signals CB and CBX.
FIG. 3 is a block diagram which shows a flow of instructions and data when the burn-in test is carried out for a microprocessor which employs a method of executing internal logic operations in response to instructions generated at random by a controller. A microprocessor 13 shown in FIG. 3 includes an input unit 14 establishing an interface with an external bus, an output interface 15, establishing an interface with the same or another external bus, and arithmetic and logic units 16-18 (hereinafter simply referred to as operation units). For example, the operation units 16-18 are an adder, a subtracter and a multiplier, respectively. Further, the microprocessor 13 includes a register file unit 19 and an address generator 20. The register file unit 19 temporarily stores operands to be supplied to the operation units 16-18 and the operation results supplied therefrom. The address generator 20 generates an address in, for example, the register file unit 19.
A controller 21 controls the operation units 16-18 and the address generator 20. An operation operand data generator 22 generates operation operand data used when the burn-in test is carried out (the burn-in test mode). Broken lines 23 denote internal buses specifically provided for transferring instructions in the burn-in test mode. The arrows added to the broken lines shown in FIG. 3 indicate the directions of flow of instructions. Solid lines 24-27 are internal buses specifically provided for transferring data when the burn-in test is performed. The arrows added to the solid lines indicate the directions of flow of data. For the sake of simplicity, internal buses used to transfer instructions in the normal operation mode and internal buses used to transfer data in the normal operation mode are omitted.
In the burn-in test mode, the operand data generated by the operand data generator 22 is supplied to the output unit 15, the operation units 16-18, the register file unit 19, the address generator 20 and the controller 21, so that the output units 15, the operation units 16-18, the register file unit 19, the address generator 20 and the controller 21 are initialized.
In microprocessors configured so that almost all the internal transistors can be switched by means of the clock signal alone, complex setting performed in the test operation is not needed and the test can be easily performed.
However, microprocessors having a circuit configuration in which the internal logic operation is performed by applying the scan signal to the scan-in terminal have the following disadvantages. Such microprocessors have the latch circuits configured as shown in FIG. 1. More specifically, each of these latch circuits is equipped with the scan-in terminal, and hence needs a large number of transistors. This leads to an increase in the circuit scale and an increase in the chip cost.
The microprocessor configured so as to use the operand data generator 22 specifically provided for the burn-in test shown in FIG. 3 has a disadvantage in that there is a need for the internal buses 23-27 specifically used for the burn-in test and in that it is necessary to provide functional blocks such as the output unit 15, the operation units 16-18, the register file unit 19, the address generator 20 and the controller 21 with selecting circuits selecting either the paths used in the normal operation paths or the paths used in the burn-in test mode. This increases the scale of the circuit configuration and the chip cost.